Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. Both of these methods, impose equally demanding limitations on memory testers that must guarantee functionality of the memory circuits under all conditions. Moreover, these memory testers must simultaneously test many of the SDRAM memory circuits in order to meet production quotas. These simultaneous tests, however, impose parasitic loads having substantial capacitance and inductance on drive circuits of the memory tester. Consequently, these parasitic loads greatly slow rise and fall times of test waveforms applied to the memory circuits. In many cases, a slow transition time of these test waveforms may induce internal oscillation of the memory clock and control signals leading to erroneous memory circuit test failures.
A clock input buffer circuit (FIG. 5) of U.S. patent application Ser. No. 09/039,012, filed Mar. 13, 1998, now U.S. Pat. No. 6,023,181, issued Feb. 8, 2000, produces a clock pulse signal IOCLK having a rising edge or transition two gate delays after a rising edge of clock input signal CLK. This rising edge turns off transistors 221 and 227, thereby disabling a first inverter of the two gate delays. Inverter 231 applies an inverted clock pulse signal at an input terminal of delay circuit 235. Delay circuit 235 produces a low output signal after a predetermined delay, thereby turning on transistor 245 and driving terminal 229 high. This high level at the input terminal of inverter 253, the second of the gate delays, drives clock pulse signal IOCLK low again. A significant problem occurs with this clock input buffer circuit, however, when noise on clock input signal CLK causes a subsequent low-high-low transition. This low-high-low transition propagates directly through the clock input buffer circuit to clock pulse signal IOCLK, since the clock input buffer is immediately enabled by a falling edge of clock input signal CLK. This false transition causes erroneous memory circuit test failure when internal operation of the memory circuit is no longer synchronized with the memory tester.